Technology interface to GLOBALFOUNDRIES (65G), TSMC (65LP, 40LP). Analog ESD protection development for TSMC 40LP technology. Foundry PCM data analysis. Understanding switching converter topologies and digital control systems. High experience with layout design and optimization, process flow. Simulation experience with HSPICE, TCAD tools and environments, Unix design systems experience. Design and develop RFICs in BiCMOS or sub-micron IC CMOS technology, identifying and analyzing performance requirements and implementing robust, manufacturable designs with best-in-class performance. Good working knowledge of advanced CMOS and RF wafer processing technologies and process interactions that affect device yields, including Systems on Chip (SoC) with Dual Gate Oxide (DGO). Experience in ASIC design, clock/power distribution and analysis, RC extraction, timing analysis. Experience with full-custom IC layout Experience in IC layout verification (DRC) Skilled in use of EDA tools for MEMS/NEMS design and analysis. Skilled in Design and manufacturing MOS Gated Power Devices. Skilled in Carrier Lifetime Measurements, CV Measurements, Chip reliability test. Skilled in STI isolation, Trench refill, Chemical Mechanical Planarization processes. Implemented Projects: Detectors Design and manufacturing: Humidity Sensor (Integrated Capacitor), Pressure Sensor (Bulk Silicon orientation (110) Trench Gate with Carrier Storage (CS) layer IGBT simulation and optimization. ChemFET and enzyme - protein sensitive FET research. Design and manufacturing BIB (Blocked Impurity Band) Photodetector for the 12-16 micron wavelength, 64x64 array, flip chip mounting with multiplexor, cooled T=10 K. Design and manufacturing 64 cells microbolometer linear array. Simulation, design, manufacturing and testing MOS controlled thyristor (2500V, 50 A) Simulation, design, manufacturing and testing Press Pack HV-IGBT (4500V, 40 –1000A) Simulation, design and manufacturing Solar Cells made with multisilicon wafers, 11.5% efficiency Avalanche Photodiode simulation (3D Single Event Upset), design and manufacturing. Avalanche photodiode array LIDAR application design and manufacturing. Quadrant PIN photodiodes design and manufacturing, 1064 nm wavelength. Position sensitive PIN photodiode design and manufacturing. Semiconductor device models implemented with VHDL simulator Simulation and design submicron SOI MOSFET Design and manufacture SJ MOSFET Devices (CoolMOS), special development – SJ MOSFET Avalanche Ruggedness, various die edge termination structures. Design and manufacture Junction Termination Extension Variation Lateral Doping (JTE VLD), own theoretical results in design optimization ©

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跑步健身，如何選一雙合適的跑鞋？（內附預防“跑步膝”小妙招） ©

Klinika Aesthevita pod odborným vedením MUDr. Jána Pilky poskytuje služby v oblasti plastické chirurgie a estetické medicíny. NaÅ¡e pobocky najdete v Praze, Karlových Varech a Melníku. Pomáháme lidem, aby se cítili lépe, zacali milovat své telo a byli spokojeni sami se sebou. Pomáháme naÅ¡im klientum najít sebevedomí... Profile ©