I am a PHD student in Microelectronics Research Lab (Micrel), University of Bologna. I joined this lab in 2012, and started to work on design and optimization of multi-bank, multi-port 3D cache and memories for cluster-based many-core platforms. My main focus in this group has been on memory and cache hierarchies, three dimensional integration, and scalable many-core platforms. In my research I take advantage of several different tools for physical implementation, evaluation, and design space exploration.
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